IE=DISABLE_CAN_INTERRUP, SIE=DISABLE_STATUS_CHANG, INIT=NORMAL_OPERATION_, EIE=DISABLE_ERROR_INTERR, TEST=NORMAL_OPERATION_, CCE=NOACCESS, DAR=ENABLED
CAN control
| INIT | Initialization 0 (NORMAL_OPERATION_): Normal operation. 1 (INITIALIZATION): Initialization is started. On reset, software needs to initialize the CAN controller. |
| IE | Module interrupt enable 0 (DISABLE_CAN_INTERRUP): Disable CAN interrupts. The interrupt line is always HIGH. 1 (ENABLE_CAN_INTERRUPT): Enable CAN interrupts. The interrupt line is set to LOW and remains LOW until all pending interrupts are cleared. |
| SIE | Status change interrupt enable 0 (DISABLE_STATUS_CHANG): Disable status change interrupts. No status change interrupt will be generated. 1 (ENABLE_STATUS_CHANGE): Enable status change interrupts. A status change interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. |
| EIE | Error interrupt enable 0 (DISABLE_ERROR_INTERR): Disable error interrupt. No error status interrupt will be generated. 1 (ENABLE_ERROR_INTERRU): Enable error interrupt. A change in the bits BOFF or EWARN in the CANSTAT registers will generate an interrupt. |
| RESERVED | reserved |
| DAR | Disable automatic retransmission 0 (ENABLED): Automatic retransmission of disturbed messages enabled. 1 (DISABLED): Automatic retransmission disabled. |
| CCE | Configuration change enable 0 (NOACCESS): The CPU has no write access to the bit timing register. 1 (ACCESS): The CPU has write access to the CANBT register while the INIT bit is one. |
| TEST | Test mode enable 0 (NORMAL_OPERATION_): Normal operation. 1 (TEST_MODE_): Test mode. |
| RESERVED | reserved |